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advanced publication release date: april 2005 - 1 - revision a10 w682510/w682310 dual-channel voiceband codecs
w682510/w682310 - 2 - 1. general description the w682510 and w682310 are general-purpose dual channel pcm codecs with pin-selectable - law or a-law companding. the device is compliant with the itu g.712 specification. it operates from a single power supply (+5v for the w682510, +3v for the w682310) and is available in 20-pin pdip (w682510 only), ssop, and 24-pin sop package options. functions performed include digitization and reconstruction of voice signals, and band limit ing and smoothing filters required for pcm systems. the filters are compliant with itu g.712 specification. the w682510 and w682310 performance is specified over the industrial temperature range of ?40 c to +85 c. the w682510 includes an on-chip precision voltage reference and receive output buffer amplifiers, capable of driving 600 ? loads (line transformers.) the analog se ction is fully differential, reducing noise and improving the power supply rejection ra tio. the data transfer pr otocol supports either parallel or serial synchronous communications for pcm applications. the w682510 and w682310 have a build in pll that eliminates the need for a master clock and automatically determines the division ratio for the required internal clock. for fast evaluation and prototyping purposes, the w682510dk & w682310dk development kits are available. 2. features ? single power supply o 4.5v to 5.5v (w682510) o 2.7v to 3.8v (w682310) ? typical power dissipation of 35 mw, power-down mode of 5 w ? fully-differential analog circuit design ? on-chip precision reference- o w682510: 1.73v for a 0.8 dbm 0tlp at 600 ? o w682310: 1.41v reference for a 0tlp of ?3.8 dbm into 1200 ? ? pin-selectable -law and a-law companding (compliant with itu g.711) ? codec a/d and d/a filtering compliant with itu g.712 ? industrial temperature range (?40 c to +85 c) ? three packages: 20-pin ssop, 20-pin pdip, and 24-pin sop applications ? digital telephone systems ? central office equipment (gateways, switches, routers) ? pbx systems (gateways, switches) ? pabx/soho systems ? hands free system ? speakerphone devices ? voip terminals ? enterprise phones ? isdn terminals ? analog line cards
w682510/w682310 publication release date: april 2005 - 3 - revision a10 3. block diagram pll / / v ssa v ssd pui v dd power conditioning ro1 ao1 - ai1 voltage reference v ref ro2 ao2 - ai2 /a - law bclk pc m int erf ac fsr fst pcmt2 pcmt1 pcmr1 pcmr2 pcmms data t1 data r1 data t2 data r2 pll / / ro1 ao1 - ai1 ro1 ao1 - ai1 voltage reference v ref ro2 ao2 - ai2 ro2 ao2 - ai2 /a - law bclk pcm interface fsr fst pcmt2 pcmt1 pcmr1 pcmr2 pcmms data t1 data r1 data t2 data r2
w682510/w682310 - 4 - 4. table of contents 1. general description ......................................................................................................... ........ 2 1. general description ......................................................................................................... ........ 2 2. features .................................................................................................................... ..................... 2 3. block diagram ............................................................................................................... .............. 3 4. table of contents........................................................................................................... ........... 4 5. pin configuration ........................................................................................................... ............ 6 6. pin description ............................................................................................................. ................ 7 7. functional description ...................................................................................................... ..... 8 7.1. transmit path ............................................................................................................................. 8 7.1.1. ai1, ai2, ao1-, ao2-.................................................................................................... .......... 9 7.1.2. pcmt1 ................................................................................................................... ................ 9 7.1.3. pcmt2 ................................................................................................................... .............. 10 7.2. receive path ............................................................................................................................ 10 7.2.1. ro1, ro2 ................................................................................................................ ............ 10 7.2.2. pcmr1................................................................................................................... .............. 11 7.2.3. pcmr2................................................................................................................... .............. 11 7.3. power signals .......................................................................................................................... 11 7.3.1. v dd ............................................................................................................................... ......... 11 7.3.2. v ssa ............................................................................................................................... ....... 11 7.3.3. v ssd ............................................................................................................................... ....... 11 7.3.4. v ref ............................................................................................................................... ....... 12 7.3.5. pui ..................................................................................................................... .................. 12 7.4. pcm interface .......................................................................................................................... 12 7.4.1. /a-law ......................................................................................................................... ....... 12 7.4.2. bclk .................................................................................................................... ................ 13 7.4.3. fsr ..................................................................................................................... ................. 13 7.4.4. fst..................................................................................................................... .................. 13 7.4.5. pcmms ................................................................................................................... ............. 13 7.5. power state modes ................................................................................................................. 13 7.5.1. power save mode......................................................................................................... ....... 13 7.5.2. power down mode......................................................................................................... ...... 14 7.5.3. power save/down output pin state ..................................................................................... 14 8. timing diagrams ............................................................................................................. ............ 15 9. absolute maximum ratings................................................................................................... 1 9
w682510/w682310 publication release date: april 2005 - 5 - revision a10 10. electrical characteristics .............................................................................................. 20 10.1. general parameters w682510 4.5v ? 5.5v ............................................................... 20 10.2. general parameters w682310 2.7v ? 3.8v ............................................................... 20 10.3. analog signal level and gain parameters ....................................................................... 22 10.4. analog distortion and noise parameters .......................................................................... 24 10.5. analog input and output amplifier parameters ................................................................ 25 10.6. digital i/o ............................................................................................................................... .26 11. typical application circuit................................................................................................ 29 12. package drawing and dimensions................................................................................... 31 12.1. 20l (pdip) plastic dual inli ne package dimensions (w682510 only) ......................... 31 12.2. 20l ssop ? 209 mil shrink small outline package dimensions ................................. 32 12.3. 24 sop ? 300 mil .................................................................................................................. 33 13. ordering information ....................................................................................................... ... 34 14. version history ............................................................................................................ ........... 35
w682510/w682310 - 6 - 5. pin configuration 24 23 22 21 20 19 18 17 16 14 w682310 dual channel codec 1 2 3 4 5 6 7 8 9 11 sop v ref ro2 n c ro1 pui pcmms n c v dd v ssd fsr pcmr2 pcmr1 ai2 ao2 - ao1 - ai1 n c a- / law v ssa n c bclk fst pcmt2 pcmt1 10 15 12 13 20 19 18 17 16 15 14 13 12 w682310 dual channel codec 1 2 3 4 5 6 7 8 9 pdip (w682510 only), ssop v ref ro2 ro1 pui pcmms v dd v ssd fsr pcmr2 pcmr1 ai2 ao2 - ao1 - ai1 ro2 ro1 pui pcmms v dd v ssd fsr pcmr2 pcmr1 ai2 ao2 - ao1 - ai1 a / - law v ssa bclk fst pcmt2 pcmt1 10 11 w682510/ w682510/
w682510/w682310 publication release date: april 2005 - 7 - revision a10 6. pin description pin name pin # ssop pdip pin # sop functionality (ch1 = channel 1, ch2 = channel 2) v ref 1 1 this pin is used to bypass the signal ground. it needs to be decoupled to v ss through a 0.1 f ceramic decoupling capacitor. no external loads should be tied to this pin. ro2 2 2 ch2 non-inverting output of the receive smoothing filter. this pin can typically drive a 600 ? load (w682510) or 1200 ? load (w682310). ro1 3 4 ch1 non-inverting output of the receive smoothing filter. this pin can typically drive a 600 ? load (w682510) or 1200 ? load (w682310).. pui 4 5 power up input signal. when this pin is high (tied to v dd ) the part is powered up. when low (tied to v ss ) the part is powered down. pcmms 5 6 pcm mode select input (se rial or parallel data interf ace) high = parallel, low = serial v dd 6 8 power supply. this pin should be decoupled to v ss with a 0.1 f ceramic capacitor. v ssd 7 9 this is the digital supply ground. this pin should be connected to 0v. fsr 8 10 8 khz frame sync input for the pcm receive section. it can also be connected to the fst pin when transmit and receive are synchronous operations. pcmr2 9 11 ch2 pcm input data receive pin. the data needs to be synchronous with the fsr and bclk pins. pcmr1 10 12 ch1 pcm input data receive pin. the data needs to be synchronous with the fsr and bclk pins. pcmt1 11 13 ch1 pcm output data transmit pin. the output data is synchronous with the fst and bclk pins. pcmt2 12 14 ch2 pcm output data transmit pin. the output data is synchronous with the fst and bclk pins. fst 13 15 8 khz transmit frame sync input. this pin synchronizes the transmit data bytes. bclk 14 16 pcm transmit and receive bit clock input pin for ch1 and ch2 transmit. v ssa 15 18 this is the analog supply ground. this pin should be connected to 0v. /a-law 16 19 compander mode select pin. -law companding is selected when this pin is low (tied to v ss .) a-law companding is selected when pin is high (tied to v dd .) ai1 17 21 ch1 non-inverting input of the first gain stage in the transmit path. ao1- 18 22 ch1 inverting analog output of the first gain stage in the transmit path. ao2- 19 23 ch2 inverting analog output of the first gain stage in the transmit path ai2 20 24 ch2 non-inverting input of the first gain stage in the transmit path.
w682510/w682310 - 8 - 7. functional description w682510/w682310 is a single-rail, dual channel pcm codec for voiceband applications. the codec complies with the specifications of the itu-t g.712 recommendation. the codec includes two complete -law and a-law companders. the -law and a-law companders are designed to comply with the specifications of the itu-t g.711 recommendation. the block diagram in section 3 shows the main components of the w682510/w682310. the chip consists of a pcm interface, which can process the data in parallel or serial formats. the pll of the chip provides the internal clock signals and synchronizes the codec sample rate with the external frame sync frequency. the power-conditioning block provides the internal power supply for the digital and the analog section, while the voltage reference block provides a precision analog ground voltage for the analog signal processing. 8 /a - control 8 bit / f c = 3400 hz smoothing filter 1a buffer1 av=1 data r1 8 /a - control 8 bit / f c = 3400 hz smoothing filter 2a buffer2 av=1 data r2 8 /a - control ai2 ao2 - - + anti - aliasin filter 2b f c = 3400 hz anti - aliasin filter 2a f c = 200 hz high pass filter 8 bit / data t1 8 /a - control ai1 ao1 - - + anti - aliasin filter 1b f c = 3400 hz anti - aliasin filter 1a f c = 200 hz high pass filter 8 bit / data t1 8 /a - control 8 bit / f c = 3400 hz smoothing filter 1a buffer1 av=1 data r1 8 /a - control 8 bit / f c = 3400 hz smoothing filter 1a f c = 3400 hz smoothing filter 1a buffer1 av=1 data r1 8 /a - control 8 bit / f c = 3400 hz smoothing filter 2a f c = 3400 hz smoothing filter 2a buffer2 av=1 data r2 8 /a - control ai2 ai2 ao2 - - + anti - aliasing filter 2b anti - filter 2b f c = 3400 hz anti - aliasing filter 2a f c = 3400 hz anti - filter 2a f c = 200 hz high pass filter 8 bit / data t2 8 /a - control ai1 ai1 ao1 - - + anti - aliasing filter 1b anti - filter 1b f c = 3400 hz anti - aliasing filter 1a f c = 3400 hz anti - filter 1a f c = 200 hz high pass filter 8 bit / data t1 figure 7.1: the w682510 and w682310 signal path 7.1. t ransmit p ath the a-to-d path of the codec contains an analog input amplifier with externally configurable gain setting (see application examples in section 11). the transmit amplifier output is the input to the encoder section. the output of the input amplifier is fed through a low-pass filter to prevent aliasing at the switched capacitor 3.4 khz low pass filter. the 3.4 khz switched capacitor low pass filter prevents aliasing of input signals above 4 khz, due to the sampling at 8 khz. the output of the 3.4 khz low pass filter is filtered by a high pass filter with a 200 hz cut-o ff frequency. the filters are designed according to the recommendations in the g.712 itu-t specification. from the output of the high pass filter the signal is digitized. the signal is converted into a compressed 8-bit digital representation with either -law or a-
w682510/w682310 publication release date: april 2005 - 9 - revision a10 law format. the -law or a-law format is pin-selectable through the /a-law pin. the compression format can be selected according to table 7.1. table 7.1: pin-selectable compression format /a-law pin format v dd (high) a-law v ssa (low) -law the digital 8-bit -law or a-law samples are fed to the pcm interface for serial or parallel transmission at the sample rate supplied by the external frame sync fst. 7.1.1. ai1, ai2, ao1-, ao2- ai1 and ai2 are the transmit analog inputs for channels 1 and 2. ao1- and ao2- are the transmit level feedback for channels 1 and 2. ai1 and ai2 are inverting inputs for the op-amps. ao1- and ao2- are connected to the outputs of the op-amps and are used to set the level, as illustrated below. when ai1 and ai2 are not used, connect ai1 to ao1- and ai2 to ao2-. during power saving mode and power down mode, the ao1- and ao2- outputs are tied weakly to v ssa on the w682510 or are high impedance on the w682310 (see table on page 14). ao1 - ai1 - + c1 r1 r2 ao2 - ai2 - + c2 r3 r4 ch1 analog input ch2 analog input gain=r2/r1 10 r2 > 20 k ohm gain=r4/r3 10 r4 > 20 k ohm ao1 - ai1 - + c1 r1 r2 ao2 - ai2 - + c2 r3 r4 ao1 - ai1 - + c1 r1 r2 ao1 - ai1 - + c1 r1 r2 ao2 - ai2 - + c2 r3 r4 ao2 - ai2 - + c2 r3 r4 ch1 analog input ch2 analog input gain=r2/r1 10 r2 > 20 k ohm gain=r4/r3 10 r4 > 20 k ohm 7.1.2. pcmt1 the pcm signal output of channel 1 when the parallel mode is selected. the pcm output signal is sent from pcmt1 in a sequential order, synchronizing with the rising edge of the bclk signal. the msb may be output at the rising edge of the fst signal, based on the timing between bclk and fst. this output pin is in a high impedance state except during 8-bit pcm output. it is also in a high impedance state during power-saving state or power-down. when serial operation is selected, this pin is configured to be the output of the serial multiplexed two channel pcm signal. a pull-up resistor must
w682510/w682310 - 10 - be connected to this pin , as it is an open drain output. this device is compatible with the itu-t coding law and output coding format recommendation. table 7.15: pcm codes for zero and full scale -law a-law level sign bit chord bits step bits sign bit chord bits step bits + full scale 1 000 0000 1 010 1010 + zero 1 111 1111 1 101 0101 - zero 0 111 1111 0 101 0101 - full scale 0 000 0000 0 010 1010 7.1.3. pcmt2 the pcm signal output for channel 2 when the parallel mode is selected. the pcm output signal is sent from pcmt2 in a sequential order, synchronized with the rising edge of the bclk signal. the msb may be output at the rising edge of the fst signal, based on the timing between bclk and fst. this pin is in a high impedance state except during 8-bit pcm output. it is also in a high impedance state during power-saving state or power-down. when the serial operation is selected, this pin is left open. a pull-up resistor must be con nected to this pin , as it is an open drain output. this device is compatible with the itu-t coding law and output coding format recommendation. 7.2. r eceive p ath the 8-bit digital input samples for the d-to-a path are serially shifted in by the pcm interface and converted to parallel data bits. during every cycle of the frame sync fsr, the parallel data bits are fed through the pin-selectable -law or a-law expander and converted to analog samples. the mode of expansion is selected by the /a-law pin as shown in table 7.2. the analog samples are filtered by a low-pass smoothing filter with a 3.4 khz cut-off frequency, according to the itu-t g.712 specification. a sin(x)/x compensation is integrated with the low pass smoothing filter. the output of this filter is buffered to provide the receive output signal ro. 7.2.1. ro1, ro2 ro1 and ro2 are the receive analog outputs for channel 1 and channel 2. the output signal of the w682510 has an amplitude of 3.46 vpp (2.03 vpp for w682310) around the signal ground voltage (v ref ). when the digital pcm signal of +3 dbm0 is presented to pcmr1 or pcmr2, it can drive a load of 600 ohms or more at 5 v supply voltage for the w682510 and 1200 ohms at 3v supply for the w682310. during power saving mode, these outputs are at the voltage level of v ref with a high impedance. these outputs have a feature that reduces audio ?pop? noises when switching between active and inactive states and back.
w682510/w682310 publication release date: april 2005 - 11 - revision a10 7.2.2. pcmr1 the pcm signal input for channel 1 when in the parallel mode. d/a conversion is performed on the serial pcm signal input to this pin. the fsr signal, synchronous with the serial pcm signal, and the bclk signal, processes the code. then the analog output is output from the ro1 pin. the data rate of the pcm signal is equal to the frequency of the bclk signal. the pcm signal is shifted in on th e falling edge of the bclk signal. it is latched into the internal 8-bit register. the start of the pcm data (msb) is synchronized with the rising edge of fsr. in the serial mode, this pin is not used and should be connected to gnd (0v). 7.2.3. pcmr2 pcm signal input for channel 2 when the parallel mode is selected. d/a conversion is performed with the serial pcm signal input to this pin, the fsr signal, synchronous with the serial pcm signal, and the bclk signal, and then the analog output is output from the ro2 pin. the data rate of the pcm signal is equal to the frequency of the bclk signal. the pcm signal is shifted at the falling edge of the bclk signal and latched into the internal register when shifted by eight bits. the start of the pcm data (msb) is identified at the rising edge of fsr. in the serial mode this pin is used for the two channel multiplexed pcm signal input. 7.3. p ower s ignals 7.3.1. v dd the power supply for the analog and digital parts of the w682510 must be 5v +/- 10% and 2.7v to 3.8v for the w682310. this supply voltage is connected to the v dd pin. the v dd pin needs to be decoupled to ground through a 0.1 f ceramic capacitor. a power supply for an analog circuit in the system to which the device is applied should be used. a bypass capacitor of 0.1 f to 1 f with good high-frequency characteristics (low esr) and a capacitor of 10 f to 20 f should be connected between this pin and the v ssa pin if needed. 7.3.2. v ssa ground for the analog signal circuits. this ground is separate from the digital signal ground. the v ssa pin must be connected to the v ssd pin on the printed circuit board to make a common ground. however, it?s advised to connect the pcb traces of these pins at the main supply hookup of the pcb and run the v ssa and v ssd traces separately to the device. 7.3.3. v ssd ground for the digital signal circuits. this ground is separate from the analog signal ground. the v ssd pin must be connected to the v ssa pin on the printed circuit board to make a common ground. however, it?s advised to connect the pcb traces of these pins at the main supply hookup of the pcb and run the v ssa and v ssd traces separately to the device
w682510/w682310 - 12 - 7.3.4. v ref this pin carries the signal ground voltage level and requires a bypass capacitor. a 0.1 f ceramic (with low esr for good high frequency response) capacitor needs to be connected between the v ssa pin and the v ref pin. 7.3.5. pui power up input signal. when the pui pin is set to logic ?0? level, the codec will go into power down mode. 7.4. pcm i nterface the pcm interface is controlled by pins pcmms, bclk, fsr & fst. the input data is received through the pcmr pin and the output data is transmitted through the pcmt pin. the modes of operation of the interface are shown in table 7.2. table 7.2: pcm interface mode selections pcmms pcm mode data available v dd [high] parallel mode ch1 data on pcmt1 & pcmr1 ch2 data on pcmt2 and pcmr2 (same timing as ch1) v ss [low] serial mode ch1 data followed by ch2 receive data on pcmr2 (total 16 bits) ch1 data followed by ch2 transmit data on pcmt1 (total 16 bits) 7.4.1. /a-law this pin selects the desired companding law. the codec will operate in the -law when this pin is at a logic ?0? level and in the a-law when at a logic ?1? level. the codec operates -law if the pin is left open, since this pin is internally pulled down. table 7.25: pin-selectable compression format /a-law pin format high (v dd ) a-law low (v ss ), floating -law
w682510/w682310 publication release date: april 2005 - 13 - revision a10 7.4.2. bclk this is the shift clock signal input for the pcmr1, pcmr2, pcmt1, and pcmt2 signals. the frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048 or 200 khz. setting this signal to a steady logic ?1? or ?0? sets both transmit and receive circuits to the power saving state. 7.4.3. fsr this is the receive synchronizing signal input. the required eight-bits of pcm data are selected from the pcm data signal to the pcmr1 and pcmr2 pins by the receive synchronizing signal. all timing signals in the receive section are synchronized by this synchronizing signal. this signal must be in phase with the bclk. the frequency should be 8 khz 50 ppm to guarantee the ac characteristics. this device can operate in the range of 6 khz to 9 khz, but the electrical characteristics specified in the data sheet are not guaranteed. 7.4.4. fst the transmit synchronizing signal input. the pcm output signal from pcmt1 and pcmt2 is sent in synchronization with this transmit synchronizing signal. this fst signal triggers the pll and synchronizes all timing signals of the transmit section. the synchronizing signal must be in phase with bclk. the frequency should be 8 khz 50 ppm to guarantee the ac characteristics. this device can operate in the range of 6 khz to 9 khz sample rates, but the electrical characteristics are not guaranteed. setting this signal to logic high or low drives both transmit and receive circuits to power saving state. 7.4.5. pcmms the control signal for mode selection of the pcm input and output. when this signal is high, the pcm input and output are in the parallel mode. the pcm data of ch1 and ch2 is input to pcmr1 and pcmr2, and output from pcmt1 and pcmt2, with the same timing. when this signal is at a low level, the pcm input and output are in the serial mode. the pcm data of ch1 and ch2 is input to pcmr2 and output from pcmt1 as two serial 8-bit bytes. 7.5. p ower s tate m odes 7.5.1. power save mode in the power save mode, all internal analog circuits except the internal reference are powered down. the codec automatically enters the power save mode when the fst or bclk signal is set to digital ?1? or digital ?0?; upon power up with fst and bclk signals present, it will take 2 to 10 milliseconds for the internal pll to lock. in addition to the pll lock-in time, the analog outputs will be set to the internal signal ground for 1 millisecond. this will avoid power up glitches at the outputs. the digital open drain outputs will remain at high impeda nce during this power up delay.
w682510/w682310 - 14 - 7.5.2. power down mode when the power up indicator pin, pui, is set low all internal circuits will go into the power down state. it will take 2 to 10 milliseconds for the pll to lo ck when operation is resumed with the fst and bclk signals applied and pui set high. an additional 1-millisecond delay is used to set the analog outputs to the signal ground reference in order to avoid power up glitches. the digi tal open drain outputs will remain at high impedance during this power up delay. 7.5.3. power save/down output pin state the following table shows the states of the output pins in the power save or power down mode. table 7.5: output pin states output pin product name ao1-, a02- ro1, ro2 w682510 v ssa signal ground w682310 high z signal ground
w682510/w682310 publication release date: april 2005 - 15 - revision a10 8. timing diagrams figure 8-1a. transmit side serial mode timing (pcmms=0) fst pcmt1 d0 d1 d2 d3 d4 d5 d6 msb d0 d1 d2 d3 d4 d5 d6 msb bclk figure 8-1b. receive side serial mode timing (pcmms=0) fsr pcmr2 d0 d1 d2 d3 d4 d5 d6 msb d0 d1 d2 d3 d4 d5 d6 msb bclk channel 1 transmit pcm data channel 2 transmit pcm data channel 2 receive pcm data channel 1 receive pcm data figure 8.1: serial mode pcm timing figure 8-2a. transmit side parallel mode timing (pcmms=1) fst pcmt1 pcmt2 d0 d1 d2 d3 d4 d5 d6 msb bclk figure 8-2b. receive side parallel mode timing (pcmms=1) fsr pcmr1 pcmr2 d0 d1 d2 d3 d4 d5 d6 msb bclk figure 8.2: parallel mode pcm timing
w682510/w682310 - 16 - figure 8-3a. burst mode with serial timing (pcmms=0) fst fsr pcmt1 pcmr2 d0 d1 d2 d3 d4 d5 d6 msb d0 d1 d2 d3 d4 d5 d6 msb bclk figure 8-3b. burst mode with parallel timing (pcmms=1) fst fsr pcmtx pcmrx d0 d1 d2 d3 d4 d5 d6 msb bclk channel 1 pcm data channel 2 pcm data 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 figure 8.3: burst mode pcm timing
w682510/w682310 publication release date: april 2005 - 17 - revision a10 table 8.1: pcm synchronization parameters symbol description min typ max unit f fs fst, fsr frequency --- 8 --- khz t ws fst, fsr pulse width 1 --- 7 t bclk t j fst, fsr allowable jitter 0 --- 500 nsec f bclk bclk frequency 64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, 1536, 1544, 200 khz d c bclk duty cycle 40 50 60 % t ir fsr, fst, bclk, pcmr1, pcmr2, pui, pcmms input rise time --- --- 50 nsec t if fsr, fst, bclk, pcmr1, pcmr2, pui, pcmms input fall time --- --- 50 nsec bclk t ws 8 7 6 5 4 3 2 1 fsr fst t j t bclk =1/f bcl k t fs =1/f fs d c t ir t i f figure 8.4: pcm synchronization parameters
w682510/w682310 - 18 - table 8.2: pcm timing parameters symbol description min typ max unit t ws fst, fsr pulse width t bclk --- 100 sec t xs bclk low to fst high setup time 100 --- --- nsec t sx fst high to bclk low hold time 100 --- --- nsec t sd pcmt1, pcmt2 output delay; cl = 100 pf 20 --- 200 nsec t xd1 pcmt1, pcmt2 output delay; cl = 100 pf 20 --- 200 nsec t xd2 pcmt1, pcmt2 output delay; cl = 100 pf 20 --- 200 nsec t xd3 pcmt1, pcmt2 output delay; cl = 100 pf 20 --- 200 nsec t rs bclk low to fsr high setup time 100 --- --- nsec t sr fsr high to bclk low hold time 100 --- --- nsec t ds pcmr1, pcmr2 data in setup time 100 --- --- nsec t dh pcmr1, pcmr2 data in hold time 100 --- --- nsec r tl pcmt1, pcmt2 pull-up resistor 500 --- --- ohm c tl pcmt1, pcmt2 load capacitance --- --- 100 pf figure 8-5a. transmit timing fst pcmt1 pcmt2 bclk msb d0 d1 d2 d3 d4 d5 d6 t ws t sx t xs t xd1 t sd t xd2 t xd3 figure 8-5b. receive timing fsr pcmr1 pcmr2 bclk 11 msb d0 d1 d2 d3 d4 d5 d6 t ws t sr t rs t dh t ds 10 9 8 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1 figure 8.5 pcm timing parameters
w682510/w682310 publication release date: april 2005 - 19 - revision a10 9. absolute maximum ratings table 9.1: absolute maximum ratings (packaged parts) condition value junction temperature 150 0 c storage temperature range -65 0 c to +150 0 c voltage applied to any pin (v ss - 0.3v) to (v dd + 0.3v) voltage applied to any pin (input current limited to +/-20 ma) (v ss ? 1.0v) to (v dd + 1.0v) lead temperature (soldering ? 10 seconds) 300 0 c v dd - v ss -0.5v to +6v note : exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. functional opera tion is not implied at these conditions. table 9.2: operating conditions (packaged parts) condition value industrial operating temperature -40 0 c to +85 0 c supply voltage (v dd ) w682510 5v +4.5v to +5.5v supply voltage (v dd ) w682310 3v +2.7v to +3.8v ground voltage (v ss ) 0v
w682510/w682310 - 20 - 10. electrical characteristics 10.1. g eneral p arameters w682510 4.5v ? 5.5v symbol parameters conditions min (2) typ (1) max (2) units v il input low voltage 0.0 0.8 v v ih input high voltage 2.2 v dd v v ol pcmt1, pcmt2 output low voltage r pullup >500 ? 0.0 0.2 0.4 v i dd v dd current (operating) - adc + dac no load, no signal 7 14 ma i sb v dd current (standby) fst or bclk =off; pui=v dd 800 1300 a i pd v dd current (power down) pui= v ss 1 10 a i il input low leakage current v ss 500 ? 0.0 0.2 0.4 v i dd v dd current (operating) - adc + dac no load, no signal 7.4 14 ma i sb v dd current (standby) fst or bclk =off; pui=v dd 700 2000 a i pd v dd current (power down) pui= v ss 1 10 a i il input low leakage current v ss w682510/w682310 publication release date: april 2005 - 21 - revision a10 symbol parameters conditions min (4) typ (3) max (4) units i ih input high leakage current v ss w682510/w682310 - 22 - 10.3. a nalog s ignal l evel and g ain p arameters w682510: v dd =5v 10%; v ss =0v; t a =-40 c to +85 c; all analog signals referred to v ref ; w682310: v dd =2.7v to 3.8v; v ss =0v; t a =-40 c to +85 c; all analog signals referred to v ref ; transmit (a/d) receive (d/a) unit parameter sym. condition typ. min. max. min. max. reference level out w682510 5v l abs 0 dbm0 = +0.8 dbm @ 600 ? load 1020 hz 0.850 --- --- --- --- v rms reference level in w682510 5v t 0tlp 1020 hz 0.850 --- --- --- --- v rms reference level out w682310 3v l abs 0 dbm0 = -3.8 dbm @ 1200 ? load 1020 hz 0.500 --- --- --- --- v rms reference level out w682310 3v t 0tlp 1020 hz 0.350 --- --- --- --- v rms max. transmit level in w682510 5v t xmax 3.17 dbm0 for -law 3.14 dbm0 for a-law 1.732 1.726 --- --- --- --- --- --- --- --- v pk v pk max. transmit level in w682310 3v t xmax 3.17 dbm0 for -law 3.14 dbm0 for a-law 0.712 0.708 --- --- --- --- --- --- --- --- v pk v pk absolute gain (0 dbm0 @ 1020 hz; t a =+25 c) g abs 0 dbm0 @ 1020 hz; t a =+25 c 0 -0.2 +0.2 -0.2 +0.2 db absolute gain variation with temperature g abst t a =0 c to t a =+70 c t a =-40 c to t a =+85 c 0 -0.08 -0.1 +0.08 +0.1 -0.08 -0.1 +0.08 +0.1 db frequency response, relative to 0dbm0 @ 1020 hz g rtv 15 hz 50 hz 60 hz 200 hz 300 to 3000 hz 3300 hz 3400 hz 3600 hz 4000 hz 4600 hz to 100 khz --- --- --- --- --- --- --- --- --- --- --- --- --- -1.5 -0.20 -0.50 -0.8 --- --- --- -40 -30 -20 -0.4 +0.20 +0.20 0 0 -14 -32 -0.5 -0.5 -0.5 -0.5 -0.20 -0.50 -0.8 --- --- --- 0 0 0 0 +0.20 +0.20 0 0 -14 -30 db
w682510/w682310 publication release date: april 2005 - 23 - revision a10 gain variation vs. level tone (1020 hz relative to ?10 dbm0) g lt +3 to ?40 dbm0 -40 to ?50 dbm0 -50 to ?55 dbm0 --- --- --- -0.3 -0.5 -1.2 +0.3 +0.5 +1.2 -0.3 -0.5 -1.2 +0.3 +0.5 +1.2 db
w682510/w682310 - 24 - 10.4. a nalog d istortion and n oise p arameters w682510: v dd =5v 10%; v ss =0v; t a =-40 c to +85 c; all analog signals referred to v ref ; w682310: v dd =2.7v to 3.8v; v ss =0v; t a =-40 c to +85 c; all analog signals referred to v ref ; transmit (a/d) receive (d/a) parameter sym. condition min. typ. max. min. typ. max. unit total distortion vs. level tone (1020 hz, -law, c-message weighted) d lt +3 dbm0 0 dbm0 to -30 dbm0 -40 dbm0 -45 dbm0 36 36 29 25 --- --- --- --- --- --- --- --- 34 36 30 25 --- --- --- --- --- --- --- --- dbc total distortion vs. level tone (1020 hz, a-law, psophometric weighted) d lta +3 dbm0 0 dbm0 to -30 dbm0 -40 dbm0 -45 dbm0 36 36 29 25 --- --- --- --- --- --- --- --- 34 36 30 25 --- --- --- --- --- --- --- --- dbp spurious out-of-band at ro- (300 hz to 3400 hz @ 0dbm0) d spo 4600 hz to 7600 hz 7600 hz to 8400 hz 8400 hz to 100000 hz --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- -30 -40 -30 db spurious in-band (700 hz to 1100 hz @ 0dbm0) d spi 300 to 3000 hz --- --- -47 --- --- -47 db intermodulation distortion (300 hz to 3400 hz ?4 to ?21 dbm0 d im two tones --- --- -41 --- --- -41 db crosstalk (1020 hz @ 0dbm0) d xt --- --- -75 --- --- -75 dbm0 channel to channel crosstalk (1020 hz @ 0dbm0) d xtch --- --- -75 --- --- -75 dbm0 absolute group delay abs 1600 hz --- --- 360 --- --- 240 sec group delay distortion (relative to group delay @ 1200 hz) d 500 hz 600 hz 1000 hz 2600 hz 2800 hz --- --- --- --- --- --- --- --- --- --- 750 380 130 130 750 --- --- --- --- --- --- --- --- --- --- 750 370 120 120 750 sec idle channel noise n idl -law; c-message a-law; psophometric --- --- --- --- 5 -69 --- --- --- --- 13 -79 dbrnc dbm0p
w682510/w682310 publication release date: april 2005 - 25 - revision a10 10.5. a nalog i nput and o utput a mplifier p arameters w682510: v dd =5v 10%; v ss =0v; t a =-40 c to +85 c; all analog signals referred to v ref ; w682310: v dd =2.7v to 3.8v; v ss =0v; t a =-40 c to +85 c; all analog signals referred to v ref ; parameter sym. condition min. typ. max. unit. ai1, ai2 input offset voltage v off,ai unity gain --- --- 20 mv ai1, ai2 input resistance r in,ai ai1, ai2 to v ref 10 --- --- m ? ao1-, ao2- output amplitude v ad w682510 w682310 0 --- 3.4 1.4 vpp ao1-, ao2- load resistance r load 20 --- --- k ? ao1-, ao2- load capacitance c load ao1-, ao2- --- --- 30 pf ro1, ro2 load resistance r load w682510 w682310 0.6 1.2 --- --- k ? ro1, ro2 load capacitance c load ro1, ro2 --- --- 50 pf ro1, ro2 output amplitude v oro w682510 w682310 --- --- 3.4 2.0 vpp ro1, ro2 output offset voltage v off,ro ro to v ref --- --- 100 mv signal ground voltage to v ssa v ref v dd /2 ? 0.1 v dd /2 v dd /2+ 0.1 v power supply rejection ratio (0 to 100 khz to v dd , c-message) psrr transmit; 50 mvpp receive; 50 mvpp -- -- 40 40 --- --- dbc
w682510/w682310 - 26 - 10.6. d igital i/o table 10.61: -law encode decode characteristics digital code d7 d6 d5 d4 d3 d2 d1 d0 normalized encode decision levels sign chord chord chord step step step step normalized decode levels 1 0 0 0 0 0 0 0 8031 : 1 0 0 0 1 1 1 1 4191 : 1 0 0 1 1 1 1 1 2079 : 1 0 1 0 1 1 1 1 1023 : 1 0 1 1 1 1 1 1 495 : 1 1 0 0 1 1 1 1 231 : 1 1 0 1 1 1 1 1 99 : 1 1 1 0 1 1 1 1 33 : 1 1 1 1 1 1 1 0 2 1 1 1 1 1 1 1 1 0 8159 7903 : 4319 4063 : 2143 2015 : 1055 991 : 511 479 : 239 223 : 103 95 : 35 31 : 3 1 0 notes: sign bit = 0 for negative values, sign bit = 1 for positive values
w682510/w682310 publication release date: april 2005 - 27 - revision a10 table 10.62: a-law encode decode characteristics digital code d7 d6 d5 d4 d3 d2 d1 d0 normalized encode decision levels sign chord chord chord step step step step normalized decode levels 1 0 1 0 1 0 1 0 4032 : 1 0 1 0 0 1 0 1 2112 : 1 0 1 1 0 1 0 1 1056 : 1 0 0 0 0 1 0 1 528 : 1 0 0 1 0 1 0 1 264 : 1 1 1 0 0 1 0 1 132 : 1 1 1 0 0 1 0 1 66 : 1 1 0 1 0 1 0 1 1 4096 3968 : 2048 2048 : 1088 1024 : 544 512 : 272 256 : 136 128 : 68 64 : 2 0 notes: 1. sign bit = 0 for negative values, sign bit = 1 for positive values 2. digital code includes inversion of all even number bits
w682510/w682310 - 28 - table 10.63: pcm codes for zero and full scale -law a-law level sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) + full scale 1 000 0000 1 010 1010 + zero 1 111 1111 1 101 0101 - zero 0 111 1111 0 101 0101 - full scale 0 000 0000 0 010 1010 table 10.64: pcm codes for 0dbm0 output -law a-law sample sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) 1 0 001 1110 0 011 0100 2 0 000 1011 0 010 0001 3 0 000 1011 0 010 0001 4 0 001 1110 0 011 0100 5 1 001 1110 1 011 0100 6 1 000 1011 1 010 0001 7 1 000 1011 1 010 0001 8 1 001 1110 1 011 0100
w682510/w682310 publication release date: april 2005 - 29 - revision a10 11. typical application circuit 0.1 ? ai2 24 ao2 - 23 ao1 - 22 ai1 21 n c 20 w682510/w2310 1 vref 2 ro2 3 nc 4 ro1 5 pui 6 pcmms 7 nc 8 v dd 9 v ssd 11 pcmr2 sop 10 fsr 12 pcmr1 a/ figure 11.1: application circuit for serial mode operation
w682510/w682310 - 30 - 0.1 w682510/w682310 1 vref 2 ro2 3 nc 4 ro1 5 pui 6 pcmms 7 nc 8 v dd 9 v ssd 11 pcmr2 sop 10 fsr 12 pcmr1 a / ? v dd 1k ? v dd pcm ch2 serial input 1k ? pcm ch2 serial output figure 11.2: application circuit for parallel mode operation
w682510/w682310 publication release date: april 2005 - 31 - revision a10 12. package drawing and dimensions 12.1. 20l (pdip) p lastic d ual i nline p ackage d imensions (w682510 only ) dimension (mm) dimension (inch) symbol min. nom. max. min. nom. max. a - - 4.45 - - 0.175 a 1 0.25 - - 0.010 - - a 2 3918 3.30 3.43 0.125 0.130 0.135 b 0.41 0.46 0.56 0.016 0.018 0.022 b 1 1.47 1.52 1.63 0.058 0.060 0.064 c 0.20 0.25 0.36 0.008 0.010 0.014 d - 20.06 26.42 - 1.026 1.046 e 7.37 7.62 7.87 0.290 0.300 0.310 e 1 6.22 6.35 6.48 0.245 0.250 0.255 e 1 2.29 2.54 2.79 0.090 0.100 0.110 l 3.05 3.30 3.56 0.120 0.130 0.140 0o - 15o 0o - 15o e a 8.51 9.02 9.53 0.335 0.355 0.375 s - - 1.91 - - 0.075 seating a e 2 a c e base 1 a 1 e l a s 1 e d 1 b b 2 1 1 1
w682510/w682310 - 32 - 12.2. 20l ssop ? 209 mil s hrink s mall o utline p ackage d imensions dimension (mm) dimension (inch) symbol min. nom. max. min. nom. max. a - - 2.00 - - 0.079 a1 0.05 - - 0.002 - - a2 1.65 1.75 1.85 0.065 0.069 - b 0.22 - 0.38 0.009 - 0.015 c 0.09 - 0.25 0.004 - 0.010 d 6.90 7.20 7.50 0.272 0.283 0.295 e 5.00 5.30 5.60 0.197 0.209 0.220 h e 7.40 7.80 8.20 0.291 0.307 0.323 e - 0.65 - - 0.0256 - l 0.55 0.75 0.95 0.021 0.030 0.037 l1 - 1.25 - - 0.050 - y - - 0.10 - - 0.004 0 0o - 8o 0 - 8o 1 2 d e e y b a a a seating dteail a l l detail a seating e h 1 1 b
w682510/w682310 publication release date: april 2005 - 33 - revision a10 12.3. 24 sop ? 300 mil l o c e h a 1 a e b d sea t ing pla ne y 0.25 g a ug e plane e 1 24 13 12 dimension (mm) dimension (inch) symbol min. max. min. max. a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 e 7.40 7.60 0.291 0.299 d 15.20 15.60 0.598 0.614 e 1.27 bsc 0.050 bsc h e 10.00 10.65 0.394 0.419 y 0.10 0.004 l 0.10 1.27 0.016 0.050 0 0o 8o 0 8o
w682510/w682310 - 34 - 13. ordering information product number descriptor key when ordering w682510 series devices, please refer to the following part numbers. part number w682510e W682510S w682510r when ordering w682310 series devices, please refer to the following part numbers. part number w682310s w682310r for the latest product information, access winbond?s worldwide website at http://www.winbond-usa.com package type: e = 20-lead plastic dual inline package (pdip) s = 24-lead plastic small outline package (sop) r = 20-lead plastic small outline package (ssop) product family w682510 product w682510 _ package type: s = 24-lead plastic small outline package (sop) r = 20-lead plastic small outline package (ssop) product family w682310 product w682310 _
w682510/w682310 publication release date: april 2005 - 35 - revision a10 14. version history version date page description 0.31 mar 2003 all preliminary specifications 0.34 apr. 2003 updates 0.35 may 2003 frequency response updated a10 april 2005 35 add important notice important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. headquarters winbond electronics corporation america winbond electronics (shanghai) ltd. no. 4, creation rd. iii 2727 north first street, san jose, 27f, 299 yan an w. rd. shanghai, science-based industrial park, ca 95134, u.s.a. 200336 china hsinchu, taiwan tel: 1-408-9436666 tel: 86-21-62365999 tel: 886-3-5770066 fax: 1-408-5441797 fax: 86-21-62356998 fax: 886-3-5665577 http://www.winbond-usa.com/ http://www.winbond.com.tw/ taipei office winbond electronics corporation japan winbond electronics (h.k.) ltd. 9f, no. 480, pueiguang rd. 7f daini-ueno bldg. 3-7-18 unit 9-15, 22f, millennium city, neihu district shinyokohama kohokuku, no. 378 kwun tong rd., taipei, 114 taiwan yokohama, 222-0033 kowloon, hong kong tel: 886-2-81777168 tel: 81-45-4781881 tel: 852-27513100 fax: 886-2-87153579 fax: 81-45-4781800 fax: 852-27552064 please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to their respective owners. this product incorporates superflash? technology licensed from sst.

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